There is a continuing trend with the semiconductor industry to fabricate device components of integrated circuits to smaller and smaller dimensions. As the dimension of device components, such as MOS transistors, are reduced to a gate length below about 0.5 microns, new technical problems arise that result in a loss of device performance. The factors associated with the loss of performance include, but are not limited to, low source-drain breakdown voltage, sub-threshold leakage, increased junction capacitance, and threshold voltage instability. These problems, known collectively as short channel effects, are related to the electrodynamics of the transistor channel during operation. In the scaling of transistor dimensions to smaller values, an attempt is made to either keep the internal electric fields constant, or to maintain long channel characteristics by subduing the sub-threshold drain current as the drain voltage is increased. Both of these methods require adjusting the electric field in the channel, such that the peak lateral electric field of the drain depletion region is minimized.
To address the problem of threshold voltage instability the injection of hot carriers into the gate oxide must be controlled. Hot carrier injection occurs as the result of a large electric field developed in the substrate near the drain region when the transistor is operated in a saturated condition. The large electric field at the drain edge provides sufficient potential to force carriers into the transistor gate dielectric. The injected carriers increase the amount of trapped charge in the gate dielectric layer. The trap charge exerts an influence over the channel region and effectively shifts the threshold voltage of the transistor. Over time, the amount of charge trapped in the gate dielectric layer increases as the transistor is repeatedly brought to saturation conditions. Eventually, the threshold voltage is shifted to a point where the transistor can no longer be controlled by applying voltage to the gate electrode.
One solution to the problem of hot carrier injection is to form a lightly-doped drain (LDD) structure. The LDD structure includes lightly-doped source-drain regions in the substrate that are aligned with the edge of the gate electrode. Heavily-doped source and drain regions are also located in the substrate, but are laterally displaced from the gate electrode. The lightly-doped region is diffused just under the gate dielectric and produces a smaller electric field near the drain edge, thus reducing hot carrier injection into the gate dielectric. The heavily-doped source and drain regions provide a low resistance regions where ohmic contacts can be made to the transistor.
Although LDD structures effectively control hot carrier injection in very-larger-scale-integration (VLSI) transistors having gate length on the order of about 0.5 microns, with the advent of deep-submicron technology for ultra-large-scale-integration-circuits (ULSI), the LDD structure must be modified to address additional technical problems. The ULSI devices have gate lengths on the order of 0.25 to 0.1 microns. At these gate dimensions, series resistance within a transistor increases to the point of degrading the speed of a transistor. To increase the current conduction in the transistor, the lightly-doped regions of the LDD structure are replaced with heavily-doped shallow source-drain extension regions. Although the increased doping level of the source-drain extension regions relative to the LDD structure reduces the series resistance, the heavily-doped drain extension regions result in a high electric field near the drain edge. As in earlier generation VLSI transistors, the increased electric field causes hot carrier injection into the gate dielectric layer.
The increased electric field near the drain edge can be reduced by lowering the doping concentration of the extension region adjacent to the drain of the transistor. For example, in the fabrication of transistors having gate lengths on the order of about 0.5 microns or larger, conventional photolithographic techniques can be used to mask the drain-side of the transistor with photoresist. Once the lithographic mask is in place, selective doping procedures can be carried out to asymmetrically dope the source-drain extension regions. Although the photolithographic technique offers a practical solution to the problem of adjusting the doping concentration in source-drain extension regions, as the gate length is scaled down to about 0.1 microns and lower it becomes more difficult to align the photoresist mask to the drain of the transistors. At the 0.1 micron level, even slight misalignment of the photolithographic mask can result in improperly doped regions in the transistor. In extreme cases, the device will fail to operate or will suffer severe performance degradation. Accordingly, an improved processing method is necessary to precisely form asymmetrically-doped source-drain extension regions in ULSI MOS transistors.